Ultra High-Density Interconnects

Cleveland Circuits Corporation is a North American leader in the electronics industry, specializing in developing and implementing ultra high-density interconnect technology for PCBs. As an early licensee of Averatek Corporation’s patented A-SAP™ Technology, Cleveland Circuits Corporation can produce ultra-fine lines and spaces in any board technology—rigid, flex, and rigid-flex—with line widths down to 25 microns. By the end of 2023, we will further advance to achieve line widths as fine as 15 microns. Cleveland Circuits Corporation utilizes Averatek Corporation’s Semi-Additive Process (A-SAP™) as a unique fabrication technique in our Ultra High-Density Interconnect program, enabling the production of ultra-fine line traces and spaces.

Design Advantages:

  • Size and Weight Reduction: Achieve dramatic reductions in size and weight compared to current state-of-the-art technologies. We currently build down to 20 microns (0.8 mil) trace and space, with 12.5 microns (0.5 mil) available later this year.
  • Tight Spacing and Impedance Control: Maintain tight spacing and impedance control (< 5%) for all line widths, including 3 mils and above.
  • Reduced Layer Count: Minimize layer count, micro vias, and lamination cycles for greater reliability.
  • Improved Signal Integrity: Achieve aspect ratios greater than 1:1 for metal traces.
  • Enhanced RF Performance: Benefit from better RF performance compared to traditional subtractive-etch processes.
  • Biocompatibility: Use gold and other noble metals as conductive materials, eliminating the need for copper or nickel.
  • Cost Reduction: Lower costs, especially for complex, high-performance boards.
Trust Cleveland Circuits Corporation to deliver cutting-edge solutions for your ultra high-density interconnect needs.
  • Less than 0.8 mm BGA Route Outs: Ideal for applications requiring routing under BGAs with less than 0.8 mm pitch.
  • Tight Impedance Tolerances < 5%: Essential for maintaining strict impedance control for high-speed and high-frequency circuits.
  • Critical Size & Weight Requirements: Perfect for designs where minimizing size and weight is crucial.
  • Interposers/Package Substrates: Suitable for advanced interposer and package substrate applications.
  • Medical Designs: Ideal for medical applications needing biocompatibility and ultra-fine features on flexible circuits.
  • Reduced Microvias: Enhances reliability by reducing the number of stacked microvias.
  • Layer Count Reduction: Simplifies designs by reducing the overall layer count.
  • Material Versatility: Compatible with a wide variety of materials, providing design flexibility.
  • Size and Weight Reduction: Achieves dramatic size and weight reductions compared to current state-of-the-art technologies.
  • Improved Reliability: Reduces layer count, microvias, and lamination cycles, enhancing overall reliability.
  • Enhanced Signal Integrity: Provides better signal integrity with aspect ratios greater than 1:1 for metal traces.
  • Superior RF Performance: Delivers improved RF performance over standard subtractive processes.
  • Biocompatibility: Allows the use of gold as a conductive metal, eliminating the need for copper and nickel, which is beneficial for medical applications.

FAQs

Yes. A-SAP™ is not limited to ultra HDI. The semi-additive process offers signal integrity benefits that make it suitable for larger feature sizes as well.

No. Both subtractive-etch layers and A-SAP™ layers can coexist in the same PCB stack-up. A hybrid approach is common, with signal layers using A-SAP™ technology to simplify the breakout of smaller BGA packages, reducing the number of layers and lamination cycles required. Layers with larger feature sizes can use traditional subtractive-etch technology.

Yes. You can design a PCB with ultra-HDI features on outer layers and connect them with reliable plated through holes using the A-SAP™ process.

There is no limit. The focus should be on designs that increase reliability by minimizing stacked vias, thus avoiding additional costs associated with processing stacked structures. Ultra-fine lines should aim to eliminate microvia structures, especially multiple stacked microvias, to enhance reliability and reduce costs.

It depends on how pads are defined by soldermask. If pads are mask-defined, spacing can be as low as 25 microns. If defined by the copper, other features need to be at least 50 microns away, preferably 75 microns. On inner layers, spacing can be 25 microns or below. For outer layers, enough space must be allowed for the soldermask to cover the trace without exposing any copper. If the mask defines the pad, 25-micron spacing works. If not, at least 50 microns of spacing is required for mask registration allowances.

Yes. The Averatek Semi-Additive Process (A-SAP™) is a proven and tested method for achieving next-generation advancements in PCB fabrication. Contact us for more information.

A-SAP™ has the potential to lower overall costs. One primary benefit of ultra HDI is the ability to reduce layer count, lamination cycles, and PCB design complexity. While A-SAP™ processing costs may be higher than subtractive etch, the overall simplification of the design can reduce total costs or provide added functionality at a similar cost.

Via-in-pad structures should be run on non-A-SAP™ layers. If needed, use these structures in an external mixed power/ground structure with limited traces and line widths of 3 mils with 5 mil spacing. If via-in-pad is necessary along with ultra-fine lines, use a copper-filled microvia to route to the next layer down. This via should be 3 to 4 mils in diameter, and the dielectric spacing should be no greater than the via diameter, preferably less, with an aspect ratio of 1:1 max. If top and bottom layers of the subassembly do not require ultra-fine line width technology, a buried via structure may be used, which can be filled and plated over.